1. Field of the Invention
The present invention relates to a method of forming silicon structures in semiconductor substrates for electronic device fabrication. More particularly, the invention provides a structure and method for fabrication of multi-layer electronic circuits including Metal Oxide Semiconductor Field Effect Transistors (MOSFETS) in any part of the bulk silicon wafer with reduced capacitance to the substrate without adverse effects of hot carrier charge build-up and floating body effects observed in conventional silicon-on-insulator (SOI) devices.
2. Description of the Related Art
Silicon-on-insulator (SOI) devices have numerous advantages for Very Large Scale Integration (VLSI) of electronic devices over conventional microelectronic circuit fabrication on bulk silicon substrate (Bulk devices). Because SOI devices are fabricated on thin silicon film on insulator, the parasitic capacitance of the source and/or drain of MOSFET to the substrate below is greatly reduced. Faster operation speed compared to bulk devices is thus assured.
The insulator on which the SOI devices are formed also changes the electric field distribution around the source/drain region and alleviates "short channel effects" (i.e. lowering of the threshold voltage of MOSFET with reduction of the channel length) which causes severe challenges for scaling down and high density packing of bulk MOSFET devices in a single chip. Additionally, device isolation of the SOI devices can be easily achieved with Shallow Trench Isolation (STI) techniques by simply etching off unnecessary parts of silicon film surrounding areas to be used for SOI devices (Active Area).
Problems to be solved
SOI substrates on which SOI devices are to be formed are generally difficult to manufacture and thus expensive compared to conventional bulk silicon substrates. In fierce competition for cost reduction of semiconductor device manufacturing, this is a great disadvantage for SOI devices. Furthermore, SOI devices have inherent drawbacks due to build-up of hot carrier generated during device operation.
During MOSFET operation, from time to time, a high electric field concentrates around the drain region. Electric carriers (i.e., electron or hole) flowing in the channel of the MOSFET are accelerated by the strong electric field around the drain and generates the opposite electric carriers (i.e., hole or electron) by impact ionization which then flows back to the body of the device. Because the SOI device is completely isolated electrically from the substrate below, the created carriers cannot be drained into the substrate and thus build up in the body of the SOI device. This is not the case for bulk devices which have an electrical path to drain carriers into the silicon substrate below. Again, because the body of the SOI device is electrically isolated, the build-up of electrical charge causes floating body effects, i.e., a shift of electrical potential in the body of SOI device with the carrier build-up. This floating body effects then induces undesirable transition in device performance such as a change of threshold voltage with time. When the build-up of the carrier in the body is large enough to apply a forward voltage between source and the body and to force forward current to flow through junction between the source and body, another electrical path away from the gate electrode is formed (parasitic bipolar action). Once this electrical path is formed, the electrical current can no longer be controlled by the gate electrode and the device becomes disabled.
FIG. 1A shows schematically a conventional n-MOSFET device in which electrons move from source to drain. Impact ionization of a hole near the drain, its flow back into the body of the MOSFET, and eventual draining to the substrate are depicted as well.
FIG. 1B shows a corresponding SOI n-MOSFET. Holes generated near the drain flow back into the substrate. However, for these holes, no draining path down to the substrate is available through the insulating oxide layer below. Holes are confined inside the SOI device body. Eventually forward voltage is applied between source and the body. Holes in the body start to flow in the source and electrons flow out of the source forming parasitic bipolar action path. With this new electron current path formed away from gate electrode besides proper channel current path at the interface between silicon and gate oxide, the SOI device shows unexpected irregular operation (a so-called "kink effect").
U.S. Pat. No. 4,763,183 to Ng et al discloses an SOI device which includes an electrically conductive pathway extending from an active area through or around the insulating region to a non-active region of the substrate. The device and its related method of manufacturing alleviate the kink-effects caused by charge accumulation. However, the process for forming the device structure requires numerous complicated steps.
Moreover, the structure and formation of the electrically conductive pathway are not satisfactory for deep sub-micron scale device fabrication. The pathway around the insulating region is apparently only attainable by sacrificing high density packaging capabilities of the electronic circuits, which is a foremost important requirement for ULSI fabrication. On the other hand, formation of electrical pathways through the insulating material requires process steps to open a small hole through the insulating region whose dimensions become less than 0.25 mm in the deep sub-micron device era (if the hole is large compared with the insulating region, the device loses advantages of SOI device). Formation of such small holes precisely aligned within the insulating region whose dimensions are less than 0.25 mm is extremely difficult and almost impractical as a ULSI manufacturing method. Furthermore, the method requires a crystallization step even for constructing a single level planar circuit which is inefficient when a single crystal plane is already available on the original substrate surface.
Accordingly, there is a need for improved devices structure and a simple fabrication method which realize high speed operation as with the conventional SOI devices but without any adverse effects related to the charge build-up and higher manufacturing cost incurred by complicated processing and expensive substrate.